Area-efficient designs for modern microprocessors, DSP's (Digital Signal Processors), SoC's (System-on-Chip) in wearables, IoTs (Internet-of-Things), smartphones, tablets, laptops, and servers, etc., are increasingly becoming a critical factor due to the following requirements: reducing silicon cost, decreasing PCB (Printed Circuit Board) footprint, improving time-to-market (TTM), and slower scaling cadence of process technology node. These requirements all need to be met while meeting the stringent frequency and/or performance targets and power/leakage budgets. One important standard cell and fundamental building block of any digital integrated circuit is the flip-flop (FF), which is required to store state in any sequential logic. Flip-flops may account for a large percentage of an integrated circuit (IC) area (e.g., greater than 30%). Flip-flops may account for a large percentage of power consumption in a clock tree and final sequential load (e.g., greater than 30%).